tools For serious firmware development, you need full source-level debugging. With source-level debugging, you can single-step through the program you develop. Kendryte has a version of the Open On-Chip Debugger (OpenOCD) software available with support for the K210 chip and Segger JLink debug probe.

JLink EDU I tested debugging the K210 on the MAiX-BiT development board with the JLink EDU probe. The cost of this debug probe is significantly lower than the professional version but is still high for a student or maker. The Open On-Chip Debugger has support for lower-cost debug probes. The current version of the Kendryte OpenOCD software only supports the JLink probe. I build a version of OpenOCD with support for both the K210 chip and the SiPEED USB-JTAG/TTL probe.

SiPEED USB-JTAG/TLL probe

On my Github, you can download the RISC-V toolchain and the OpenOCD version with Kendryte K210 support. Connect the JTAG probe to the MAiX-BiT development board, as shown in the table below. You can use the GNU debugger extension for Visual Studio Code I made for the Arm chips.

JTAG signal MAiX BiT Silk K210  
Test Data In TDI 1 IO1  
Test Reset RST RST RESET  
Test Mode Select TMS 2 IO2  
Test Data Out TDO 3 IO3  
Test Clock TCK 0 IO0  
Ground GND GND GND  

JLink EDU

I choose the colours of the wires arbitrary.

I made the following configuration file for OpenOCD.

# SiPEED USB-JTAG/TTL 
interface ftdi
ftdi_device_desc "Dual RS232"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0508 0x0f1b
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400

jtag_rclk 3000 

# server port
gdb_port 3333
telnet_port 4444

# add cpu target
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x04e4796b

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME

# command
init
if {[ info exists pulse_srst]} {
  ftdi_set_signal nSRST 0
  ftdi_set_signal nSRST 1
  ftdi_set_signal nSRST z
}
halt